Current low power double data rate fourth-generation (LPDDR4) random access memory (RAM) is expected to support data rates up to 4266 Mbps using 2133 MHz clock frequency. The design of the input data latches is important for achieving this performance level. Challenges include relatively low power supply levels and minuscule input signal energy. Inter-symbol interference (ISI) caused by lossy routes, reflections due to characteristic impedance discontinuities, and crosstalk between parallel signal lines, as well as clock jitter, degrade an input signal to the point that an input data latch should resolve pulses of less than 80 ps by 50 mV. Traditional sense-amplifier latches already have difficulties operating under these conditions and show relatively poor rank margin tool (RMT) margins. An option for input data latches is to use decision feedback equalization (DFE). Typical low overhead DFE receiver implementations involve an analog loop, which applies the feedback to either the input or the reference voltage. The speed of these receivers is limited by the bandwidth and latency of the analog feedback.